1. Field of the Invention
The present invention relates to a read circuit of dynamic random access memory.
2. Prior Art
A bit of memory cell in a dynamic random access memory (DRAM) consists for example of a capacitor for storing charges (information) and a switch for selecting the memory cell (address), and information of logic "1" and "0" is stored as charges are or are not stored in the capacitor. A large number of memory cells is arranged as a matrix at crossings of bit lines and word lines. A memory cell is selected by designating its address which is determined by a word line and a data line, and the information is read by turning on the switch to connect the capacitor to a bit line and by sensing a change in the potential of the bit line according to the charges stored in the capacitor.
In a DRAM of large capacity such as 64 MB, each memory cell has to be designed to have a small size, and a very large number of memory cells is connected to each bit line. Therefore, a ratio of the capacitance C.sub.a of the capacitor to the stray capacitance C.sub.b of the bit line becomes very small, and a change in the potential of the hit line becomes small and harder to sense.
In order to solve this problem, a bit line is multiply divided or a memory array is divided into a plurality of memory arrays in the direction of a bit line so as to reduce the number of memory cells connected to the bit line in each memory array, so that a ratio C.sub.a /C.sub.b is reduced to a desired value. Further, in order to prevent the increase in area due to peripheral circuits such as decoders, a common selection signal line for selecting a bit line is connected so as to provide a selection signal of a bit line to the memory arrays.
In addition, in order to reduce the dissipation of electric power, sense amplifier circuits of DRAM are controlled so that only a sense amplifier circuit in correspondence to a memory array including a memory cell to be selected is activated.
FIG. 1 displays a circuit diagram of a portion of a prior art sense amplifier of DRAM which has a flip flop type sense amplifier of cross coupling type. In this amplifier, four MOSFETs (Q8, Q9, Q10 and Q11) for amplification are cross coupled to bit lines D and D.
Recently, in a non-address-multiplex type dynamic random access memory (DRAM) (refer to K. Yanagisawa et al., ESSCIRC pp. 184-187) and in a low voltage 64 MB DRAM (Y. Nakagome et al., 1990 SYMPOSIUM ON VLSI CIRCUITS pp. 17-18), a new type of sense amplifier circuit is added besides the above-mentioned flip-flop type sense amplifier circuit, as shown also in FIG. 1. The new sense amplifier includes three transistors Q1, Q2 and Q3 in order to isolate the bit lines and the common data lines. That is, the potentials of the bit lines D and D are provided to the gates of the transistors Q1, Q2 while the column decode line YS is connected to the gate of the transistor Q3. The source electrodes of the transistors Q1 and Q2 are connected to the common data lines CD and CD of a precharger, while the drain electrodes of the transistors Q1 and Q2 are connected to the source electrode of the transistor Q3. The drain of the transistor Q3 is connected to the ground. Thus, the ground and the common data lines CD, CD are connected via the on resistance of the MOSFET (Q3).
The background of the introduction of this new technique is as follows: The stray capacitance of the common data line increases while the current driving force of sense amplifying transistors Q8-Q11 becomes smaller with an increase in the degree of integration of DRAM. Therefore, when bit lines and common data lines are connected via a switch, the data of the bit line is destroyed before the potential at the bit line is amplified sufficiently. Thus, in order to operate the reading function with the new sense amplifier circuit, it is necessary to isolate the bit lines from the common data lines electrically.
However, as mentioned above, when a selection signal of a data line in a plurality of memory arrays is generated by a common address decoder, the common data lines are connected to the ground even in the memory array parts not selected. At this time, because the common data lines are kept at the half precharge level (V.sub.cc /2) or higher, the potential levels at the common data lines vary by a large amount. Thus, as shown with an arrow in FIG. 1, a through current flows to the ground via precharger circuits connected to the common data lines and to the transistors Q1-Q3 in the memory array parts not selected. Therefore, it is a problem to reduce the dissipation current in order to decrease the dissipation in a highly integrated DRAM.